A Systolic Array-Based FPGA Parallel Architecture for the BLAST Algorithm
نویسندگان
چکیده
منابع مشابه
A Systolic Array-Based FPGA Parallel Architecture for the BLAST Algorithm
A design of systolic array-based Field Programmable Gate Array (FPGA) parallel architecture for Basic Local Alignment Search Tool (BLAST) Algorithm is proposed. BLAST is a heuristic biological sequence alignment algorithm which has been used by bioinformatics experts. In contrast to other designs that detect at most one hit in one-clock-cycle, our design applies a Multiple Hits Detection Module...
متن کاملDesign and FPGA Implementation of Systolic Array Architecture for Full Search Block Matching Algorithm
In digital video coding applications, adjacent frames look similar and changes are due to the movement of the object or the camera. So their spatial and temporal redundancy must be exploited to obtain reduced data to store and transmit. The motion between two consecutive images can be estimated using Full Search Block Matching Algorithm (FSBMA). This algorithm determines motion by pixel-by-pixe...
متن کاملImplementation of Systolic Array Architecture for Full Search Block Matching Algorithm on FPGA
Today’s technological growth in the semiconductor industry has created unprecedented demand for electronic gadgets that are very sophisticated and user friendly. Interfaces with audio/video capabilities have further enhanced the demand for the products in the market. Video data needs to be compressed before storage and transmission; complex algorithms are required to eliminate the redundancy, e...
متن کاملFPGA-Based Configurable Systolic Architecture for Window-Based Image Processing
Image processing requires more computational power and data throughput than most conventional processors can provide. Designing specific hardware can improve execution time and achieve better performance per unit of silicon area. A fieldprogrammable-gate-array(FPGA-) based configurable systolic architecture specially tailored for real-time window-based image operations is presented in this pape...
متن کاملAn FPGA architecture for DRAM-based systolic computations
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serve. Wide data paths within the chip are time multiplexed at the edge of the chip into much faster and narrower data paths that run offchip. This kind of arrangement makes it possible to interface a relatively slow FPGA ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: ISRN Bioinformatics
سال: 2012
ISSN: 2090-7346
DOI: 10.5402/2012/195658